A Journey from Immersion Lithography to EUVL

CK Chen^1,2*

¹Technology Development Center, ASML, Hsinchu, Taiwan
²College of Semiconductor Research, National Tsing Hua University, Hsinchu, Taiwan

* Presenter:CK Chen, email:ck.chen@asml.com

Moore’s law, the number of transistors doubling every two years, has been the driving force for semiconductor innovations on device architecture evolutions and lithography scaling techniques. The wavelength-driven lithography machines through g-line(436nm), i-line(365nm), KrF(248nm), ArF(193nm), immersion ArF(134nm), and EUV(13.5nm) sustain chip scaling of integrated circuits (ICs) to have better power efficiency, higher clock speed, and smaller chip area every two years. In the period of between 2000 and 2010, immersion lithography was proposed and developing for the high volume manufacturing (HVM) of IC chips. And, in the ten years it beat out the potential candidate of wavelength of 157nm, a possible successor after 193nm. At the end, the immersion lithography became a major workhorse for the nodes of 40nm in 2008 to 7nm in 2018 instead of ArF. In 2010, the first EUV tool was shipment in industry for early study and engagement. In 2020, EUV machine joined the HVM of IC chips at 5nm node becoming a major workhorse for the upcoming couples of decades. It starts a new era in photo-lithography to have one order of magnitude smaller wavelength than that of immersion lithography. It keeps Moore’s law still driving in the era of Artificial Intelligence, machine learning, 5G, data center and cloud computing.

Keywords: Lithography, immersion , EUV, Moore's Law, Semiconductor