Approaching High-Performance Two-Dimensional Transistors by a van der Waals Bottom Contact Structure

Yuan-Chun Su^1*, Po-Husn Ho², Yu-Chen Chang¹, Yi-Hsiu Huang³, Chao-Ching Cheng², Chao-Hsin Chien³, Wen-Hao Chang^1,4

¹Department of Electrophysics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
²Corporate Research, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
³Department of Electronics Engineering and the Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan
⁴Research Center for Applied Sciences, Academia Sinica, Taipei, Taiwan

* Presenter:Yuan-Chun Su, email:eric8802050205@gmail.com

Two-dimensional (2D) semiconductors have been considered as promising candidates of nanometer-thin channel materials for nanoelectronics. However, controlling the polarity of transistors based on 2D materials via selecting different contact metals only shows very limited success due to fermi-level pinning at the interface between metal and 2D materials. Here, we report a new approach for fabricating 2D-materials transistors using a van der Waals (vdWs) bottom contact-structure. The device structure is free from defects formed during metal depositions, which can mitigate the fermi-level pinning effects and hence enable n-type and p-type doping at both contact and channel regions to improve the device performance through solution-based surface charge transfer doping. In addition, this structure also provides a clean interface without chemical disorder for high quality atomic layer deposition (ALD). A sub-8nm high-k dielectric layer was deposited on top of a monolayer MoS2 channel to form a dual-gate field effect transistor. The electrostatically doped spacers in the bottom contact structure can well control 2D-material transport type and improve the device performance, paving the way for developing 2D transistors.

Keywords: 2D semiconductors, dual gate, Doping, MoS2